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          数电的最后lab--简易CPU
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        <h2 id="1-设计目的"><a href="#1-设计目的" class="headerlink" title="1.设计目的"></a>1.设计目的</h2><ol>
<li><p>力图以“培养学生现代数字系统设计能力”为目标，贯彻以CPU设计为核心，以层次化、模块化设计方法为抓手的组织思路，培养学生设计与实现数字系统的能力，本设计要求在进行了多个单元实验后，综合利用所学的理论知识，并结合在单元实验中所积累的成果（包括已经设计好的功能部件和调试方法），设计出一个简易计算机系统。</p>
</li>
<li><p>完整、连贯地运用《数字逻辑》所学到的知识，熟练掌握 EDA 工具基本使用方法，为 学习好后续《计算机原理》课程做铺垫。</p>
</li>
</ol>
<h2 id="2-设计内容"><a href="#2-设计内容" class="headerlink" title="2.设计内容"></a>2.设计内容</h2><ol>
<li>按照给定的数据通路、数据格式和指令系统，使用 EDA 工具设计一台用硬连线逻辑控制的简易计算机。</li>
<li>对给出的模型机的各个部件进行设计，进行模块化封装后进行连接整合成简易计算机。</li>
<li>要求灵活运用各方面知识，使得所设计的计算机系统具有较佳的性能。</li>
<li>模型机各个部件如SM，IR，ALU等进行设计。</li>
<li>对所做设计的性能指标进行分析，整理出设计报告。</li>
</ol>
<a id="more"></a>

<h2 id="3-详细设计"><a href="#3-详细设计" class="headerlink" title="3.详细设计"></a>3.详细设计</h2><h3 id="3-1设计的整体构架"><a href="#3-1设计的整体构架" class="headerlink" title="3.1设计的整体构架"></a>3.1设计的整体构架</h3><p>计算机的工作过程可以看作是许多不同的数据流和控制流在机器各部分之间的流动，数 据流所经过的路径称作机器的数据通路。</p>
<img src="https://i.loli.net/2021/04/14/wbaPthxmZXW7du2.png" alt="数据通路" style="zoom:80%;" />

<p><img src="https://i.loli.net/2021/04/14/SvDptUdCKmJo2Zf.png" alt="全"></p>
<h3 id="3-2各模块的具体实现"><a href="#3-2各模块的具体实现" class="headerlink" title="3.2各模块的具体实现"></a>3.2各模块的具体实现</h3><h4 id="1-指令译码器与控制信号产生逻辑"><a href="#1-指令译码器与控制信号产生逻辑" class="headerlink" title="1.指令译码器与控制信号产生逻辑"></a>1.指令译码器与控制信号产生逻辑</h4><h5 id="接口实现"><a href="#接口实现" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/07/13/Epyzvw17rt9AF6i.png" alt="cd"></p>
<p>IR1,IR2为指令寄存器传来的数据，EN为使能端口，与SM相连。</p>
<p><img src="https://i.loli.net/2021/04/14/VTUf2NQqd96GAZL.png" alt="ctrol"></p>
<table>
<thead>
<tr>
<th>输入端口</th>
<th>功能</th>
<th>输出端口</th>
<th>功能</th>
</tr>
</thead>
<tbody><tr>
<td>MOVA</td>
<td>（R2）→ R1指令译码器输出的控制信号</td>
<td>RAA 2位</td>
<td>为向通用寄存器组产生的控制信号</td>
</tr>
<tr>
<td>MOVB</td>
<td>（R2）→（C）指令译码器输出的控制信号</td>
<td>RWBA2位</td>
<td>为向通用寄存器组产生的控制信号</td>
</tr>
<tr>
<td>ADD</td>
<td>（R1）+（R2）→ R1</td>
<td>WE</td>
<td>允许把 BUS 上的数据打入通用寄存器组，低电平有效。</td>
</tr>
<tr>
<td>SUB</td>
<td>（R1）-（R2）→ R1</td>
<td>ALUS</td>
<td>向ALU函数发生器产生的控制信号，允许进行运算</td>
</tr>
<tr>
<td>OR0</td>
<td>（R1）∨（R2）→ R1</td>
<td>M(ALUM)</td>
<td>ALU使能</td>
</tr>
<tr>
<td>NOT0</td>
<td>/（R1）→ R1</td>
<td>FBUS</td>
<td>移位逻辑使能</td>
</tr>
<tr>
<td>SHR</td>
<td>（R1）循环右移一位→ R1</td>
<td>FRBUS</td>
<td>移位逻辑右移位</td>
</tr>
<tr>
<td>SHL</td>
<td>（R1）循环左移一位→ R1</td>
<td>FLBUS</td>
<td>移位逻辑左移位</td>
</tr>
<tr>
<td>JMP</td>
<td>add → PC</td>
<td>LDPC</td>
<td>向指令计数器PC发出的加一操作信号。</td>
</tr>
</tbody></table>
<table>
<thead>
<tr>
<th>输入端口</th>
<th>功能</th>
<th>输出端口</th>
<th>功能</th>
</tr>
</thead>
<tbody><tr>
<td>JZ</td>
<td>结果为 0 时 add → PC</td>
<td>INPC</td>
<td>向指令计数器PC发出的跳转操作信号。</td>
</tr>
<tr>
<td>JC</td>
<td>结果有进位时 add → PC</td>
<td>MADD 2位</td>
<td>指向选择器的控制信号。</td>
</tr>
<tr>
<td>IN0</td>
<td>（开关 7-0）→ R1</td>
<td>XL</td>
<td>向RAM发出的控制信号，XL为向RAM进行读操作。</td>
</tr>
<tr>
<td>OUT0</td>
<td>（R1）→ 发光二极管 7-0</td>
<td>DL</td>
<td>向RAM发出的控制信号，DL为进行操作为写操作。</td>
</tr>
<tr>
<td>NOF</td>
<td>空操作指令</td>
<td>LDIR</td>
<td>为向指令寄存器IR发出的控制信号</td>
</tr>
<tr>
<td>HALF</td>
<td>停机</td>
<td>CFEN</td>
<td>N为对C,Z寄存器的使能信号，使其工作。</td>
</tr>
<tr>
<td>IR 8位</td>
<td>指令寄存器传送的RAM数据，指令译码器输出的控制信号</td>
<td>ZFEN</td>
<td></td>
</tr>
<tr>
<td>SM</td>
<td>SM传送的时钟信号端口</td>
<td>INEN</td>
<td>指令译码器的控制信号</td>
</tr>
<tr>
<td>Cf,Zf</td>
<td>触发器</td>
<td>SMEN</td>
<td>时钟使能</td>
</tr>
</tbody></table>
<h5 id="功能实现"><a href="#功能实现" class="headerlink" title="功能实现"></a>功能实现</h5><ol>
<li><p>通过指令系统表我们可以设计一个由指令码映射到指令信号的译码器。其中 指令码为 8 位二进制码，译码器的输出端为指令操作。</p>
</li>
<li><p>指令寄存器 IR 接收到一条机器指令后，这条指令就被译码执行。指令通过译码产生出 的各种控制信号在时钟信号的配合下控制着指令执行的全过程。为此，需要将执行每条指令 所需的全部基本微操作的控制信号罗列出来，进行综合分析、化简，并落实到不同的周期、 节拍之中，然后用各种逻辑门电路实现。</p>
<p>控制信号表：</p>
</li>
</ol>
<img src="https://i.loli.net/2021/04/14/hOpNZsMSHyfIXql.png" alt="cdfunc" style="zoom:80%;" />

<img src="https://i.loli.net/2021/04/14/CgG5Ku4PmbVZqEz.png" alt="ctrolfunc" style="zoom: 80%;" />

<h5 id="仿真验证"><a href="#仿真验证" class="headerlink" title="仿真验证"></a>仿真验证</h5><p><img src="https://i.loli.net/2021/04/14/8LqmcwKP4oJ93Os.png" alt="cdfug"></p>
<p>1.0-30ns 输入00000000，使能恒为1。不输出值。</p>
<p>2.30-50ns 输入11110000，对应MOVB，MOVB为1,，正确。</p>
<p>3.60-80ns 输入11110011，对应MOVC为1，正确。</p>
<p>4.80-110ns 输入11110000，对应MOVA为1，正确。</p>
<p>5.220-250ns 输入01100000，对应SUB为1，正确。</p>
<p>6.280-330ns 输入10110000，对应OR0为1，正确</p>
<p>7.140-180ns 输入10010000，对应ADD为1，正确</p>
<p>8.350-400ns 输入01010000，对应NOT0为1，正确</p>
<p>9.420-460ns 输入10100000，对应RSR为1，正确</p>
<p>10.460-490ns 输入10100011，对应RSL为1，正确</p>
<p>11.510-530ns 输入00110000，对应JMP为1，正确</p>
<p>12.530-550ns 输入00110001，对应JZ为1，正确</p>
<p>13.560-590ns 输入00110010，对应JC为1，正确</p>
<p>14.610-680ns 输入00100000，对应IN0为1，正确</p>
<p>15.700-760ns 输入01000000，对应OUT0为1，正确</p>
<p>16.780-840 ns 输入01110000，对应NOP为1，正确</p>
<p>17.870-940ns 输入10000000，对应HALT为1，正确</p>
<h4 id="2-8位3-1多路复用器"><a href="#2-8位3-1多路复用器" class="headerlink" title="2.8位3-1多路复用器"></a>2.8位3-1多路复用器</h4><h5 id="接口实现-1"><a href="#接口实现-1" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/04/14/iTj9KQRyFpZnzqc.png" alt="mux3-1"></p>
<h5 id="功能实现-1"><a href="#功能实现-1" class="headerlink" title="功能实现"></a>功能实现</h5><p>输入端为来自S,D以及PC传来的数据，进行选择传输到RAM中。</p>
<h5 id="仿真验证-1"><a href="#仿真验证-1" class="headerlink" title="仿真验证"></a>仿真验证</h5><img src="https://i.loli.net/2021/04/14/ZNxHIuiEhORn2fL.png" alt="lab2.1"  />

<p>输入为in0,in1,in2,3个8位输入。</p>
<p>t=0-420ns，当in0=10000001时，S=00时，Y=10000001，正确</p>
<p>t=0-420ns，当in1=11111110时，S=01时，Y=10000001，正确</p>
<p>t=0-420ns，当in2=00010101时，S=10时，Y=00010101，正确</p>
<h4 id="3-函数发生器ALU"><a href="#3-函数发生器ALU" class="headerlink" title="3.函数发生器ALU"></a>3.函数发生器ALU</h4><h5 id="接口实现-2"><a href="#接口实现-2" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/04/14/O8c1fzBlpgYxayF.png" alt="ALUG"></p>
<h5 id="功能实现-2"><a href="#功能实现-2" class="headerlink" title="功能实现"></a>功能实现</h5><p>算术逻辑运算类指令： ADD R1, R2 SUB R1, R2 OR R1, R2 S D S D NOT R1 这类指令的执行过程为： 由R2的编码通过RAA1、RAA0 从通用寄存器组S口读出R2的内容,由R1的 编码通过RWBA1、RWBA0从通用寄存器组D口读出R1的内容，在S3～S0和M的 控制下，实现运算，经移位逻辑送入总线BUS；由/WE控制和R1的编码选择RWBA1、RWBA0，将BUS上的数据写入通用寄存器R1。其中ADD和SUB指令影 响状态位Cf和Zf。</p>
<p>alu要实现从通用寄存器组通过RAA1与RAA0指令从S口读取R2，D口读出R1，要求输入从S0-S3来控制实现指令运算，M是EN端口，Cf为加法或减法进借位，Zf为若两个数相减为0则输出1。</p>
<table>
<thead>
<tr>
<th>符号</th>
<th>功能</th>
</tr>
</thead>
<tbody><tr>
<td>ADD</td>
<td>将R1+R2的值赋予R1</td>
</tr>
<tr>
<td>SUB</td>
<td>将R1-R2的值赋予R1</td>
</tr>
<tr>
<td>OR</td>
<td>R1与R2进行与运算的值赋R1</td>
</tr>
<tr>
<td>NOT</td>
<td>进行取反运算，将R1非的值赋予R1</td>
</tr>
</tbody></table>
<p>当S=1001，ADD S=0110 SUB，S=1011 OR ，S=0101 OR</p>
<p>其中将ALU的中间信号temp增添一位变成9位，防止溢出，将最高位直接赋值Cf操作。</p>
<p>若为加法Zf直接输出0，另外，ALU在MOVA、MOVB、RSR、RSL和OUT 五条指令执行时，将输入S或D口的数据传输至输出T，提供将数据传输至 BUS 总线的数据通路。则S=1010进行移位操作时，ALU要提供数据通路，将S或D对T进行赋值。</p>
<h5 id="仿真验证-2"><a href="#仿真验证-2" class="headerlink" title="仿真验证"></a>仿真验证</h5><img src="https://i.loli.net/2021/04/14/YJwuQlxBS3pTPzh.png" alt="2"  />

<p>M为使能端口</p>
<p>M=1</p>
<p>sn=1001，D=10100001,S=10101001,T=01001010,Cf=1;</p>
<p>sn=0110，D=10111000,S=11010000,T=11101000,Cf=1,D=11111111,S=111111111,T=00000000,Zf=1;</p>
<p>sn=1011，D=10101100,S=10100011,T=10101111,T=10101111；</p>
<p>后序功能传输数据正常</p>
<h4 id="4-移位逻辑"><a href="#4-移位逻辑" class="headerlink" title="4.移位逻辑"></a>4.移位逻辑</h4><h5 id="接口实现-3"><a href="#接口实现-3" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/04/14/37D5KOPLwUQCm1j.png" alt="shift"></p>
<h5 id="功能实现-3"><a href="#功能实现-3" class="headerlink" title="功能实现"></a>功能实现</h5><p>移位指令： RSR R1 RSL R1 这类指令的执行过程为： 由R1的编码通过RWBA1、RWBA0从通用寄存器组D口读出R1的内容，在 S3~S0和M的控制下通过ALU，经移位逻辑循环右移或循环左移后送入总线BUS再由/WE控制和R1的编码选择RWBA1、RWBA0，将BUS上的数据写入通用寄存器R1。</p>
<p>1.由R1的编码通过RWBA1、RWBA0从通用寄存器组D口读出R1的内容，在 S3~S0和M的控制下通过ALU，经移位逻辑循环右移或循环左移后送入总线BUS； 再由/WE控制和R1的编码选择RWBA1、RWBA0，将BUS上的数据写入通用寄存器R1。</p>
<table>
<thead>
<tr>
<th>flbus</th>
<th>左移信号</th>
</tr>
</thead>
<tbody><tr>
<td>fbus</td>
<td>使能端口</td>
</tr>
<tr>
<td>frbus</td>
<td>右移信号</td>
</tr>
</tbody></table>
<p>2.RSR 循环移位操作具体如下：</p>
<p><img src="https://i.loli.net/2021/04/14/VhKRMvPko9bi2gq.png" alt="4"></p>
<p>3.移位逻辑需要实现RSR、RSL操作，还需提供MOVA、MOVB、ADD、SUB、 OR、NOT、OUT指令执行时,将数据传输至BUS总线的通路。</p>
<p>4.右移直接将A0赋值给Cf，左移将A7赋值Cf。</p>
<p>5.当使能为0时，输出高阻态。</p>
<h5 id="仿真验证-3"><a href="#仿真验证-3" class="headerlink" title="仿真验证"></a>仿真验证</h5><p><img src="https://i.loli.net/2021/04/14/G8HoP6frSBmz9IK.png" alt="6"></p>
<p>A=10101011</p>
<p>FBUS=1</p>
<p>FLBUS=1,w=010110111,Cf=1,FRBUS=1,w=11010101;</p>
<p>FLBUS=0,w=ZZZZZZZZ。</p>
<h4 id="5-CF-ZF触发器"><a href="#5-CF-ZF触发器" class="headerlink" title="5.CF,ZF触发器"></a>5.CF,ZF触发器</h4><h5 id="接口实现-4"><a href="#接口实现-4" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/04/14/ktoiBVs1RcLHhan.png" alt="Cf"></p>
<p><img src="https://i.loli.net/2021/04/14/87QhbDeIia5UlWx.png" alt="zf"></p>
<h5 id="功能实现-4"><a href="#功能实现-4" class="headerlink" title="功能实现"></a>功能实现</h5><p>当时钟下边沿到来时，且使能端为1时，将输入赋予Zf,Cf。</p>
<h5 id="仿真验证-4"><a href="#仿真验证-4" class="headerlink" title="仿真验证"></a>仿真验证</h5><p><img src="https://i.loli.net/2021/04/14/nhfcHw3i78ClJQj.png" alt="CFfunc"></p>
<h4 id="6-IR寄存器"><a href="#6-IR寄存器" class="headerlink" title="6.IR寄存器"></a>6.IR寄存器</h4><h5 id="接口实现-5"><a href="#接口实现-5" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/04/14/KEmeFwdVc36Jvq7.png" alt="IR"></p>
<h5 id="功能实现-5"><a href="#功能实现-5" class="headerlink" title="功能实现"></a>功能实现</h5><p>将指令寄存到IR寄存器中，当时钟下边沿到来且ld=1时，高四位传给a口，第四位传给b口，全8位传给R口。</p>
<p>LD IR 允许把 BUS 上的数据打入指令寄存器 IR。</p>
<h5 id="仿真验证-5"><a href="#仿真验证-5" class="headerlink" title="仿真验证"></a>仿真验证</h5><p><img src="https://i.loli.net/2021/04/14/rVdhk3SJsgTY7MU.png" alt="IRfunc"></p>
<p>t=400ns时，时钟下边沿到来，输入11010011，同时ld=1，输出a高四位1101，b输出第四位0011，R输出11010011；</p>
<h4 id="7-通用寄存器组"><a href="#7-通用寄存器组" class="headerlink" title="7.通用寄存器组"></a>7.通用寄存器组</h4><h5 id="接口实现-6"><a href="#接口实现-6" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/04/14/gdpjKNlVs8aUvbZ.png" alt="SRG"></p>
<h5 id="功能实现-6"><a href="#功能实现-6" class="headerlink" title="功能实现"></a>功能实现</h5><p>寄存器是CPU内的重要组成部分，模型机的通用寄存器组包含3个8位寄存器 A、B、C，实现对此3个寄存器的读写操作。其接口及功能如下：</p>
<table>
<thead>
<tr>
<th>操作</th>
<th>CLK</th>
<th>WE</th>
<th>RAA[1..0]</th>
<th>RWBA[1..0]</th>
<th>功能</th>
</tr>
</thead>
<tbody><tr>
<td>读</td>
<td></td>
<td></td>
<td>00或01或 10</td>
<td>00或01或10</td>
<td>根据RAA[1..0]的值从A,B,C中选择 一个寄存器的值由S口输出 根据RWBA[1..0]的值从A,B,C中选 择一个寄存器的值由D口输出</td>
</tr>
<tr>
<td>写</td>
<td>下边沿</td>
<td>0</td>
<td>XX</td>
<td>00或01或10</td>
<td>控制信号WE为0，根据RWBA[1..0] 的值, 在时钟下降沿将外部输入写 入A,B,C三个寄存器中的某个寄存 器。</td>
</tr>
</tbody></table>
<h5 id="仿真验证-6"><a href="#仿真验证-6" class="headerlink" title="仿真验证"></a>仿真验证</h5><p><img src="https://i.loli.net/2021/04/14/76O8uwU94gqKzrt.png" alt="9"></p>
<p>寄存器组需要完成读取操作，写入操作，2种操作需要同时进行。</p>
<p>写操作当时钟下边沿触发，t=50ns时，输入I=1111000，RA=00,WA=00，将I中数据写入到A寄存器中，同时进行输出操作，由于RA=00,WA=00，同时将A寄存器中的数据分别读取到S,D口。</p>
<p>t=130ns时，输入改变为10000000，WA=01，此时将I中数据写入B寄存器，由于RA=00，将A寄存器数据读取到S口，B寄存器数据读取到D口。</p>
<p>t=260ns时，输入改变为01010001，RA=00，WA=10，将I中数据写入C寄存器中，同时将A寄存器数据读取到S口，C寄存器数据读取到D口。</p>
<h4 id="8-指令计数器PC"><a href="#8-指令计数器PC" class="headerlink" title="8.指令计数器PC"></a>8.指令计数器PC</h4><h5 id="接口实现-7"><a href="#接口实现-7" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/04/14/JEIl85uQa6tOSzy.png" alt="PC"></p>
<h5 id="功能实现-7"><a href="#功能实现-7" class="headerlink" title="功能实现"></a>功能实现</h5><p>指令计数器PC保存的是下一条指令在RAM中存放的地址。 CPU执行一条指令，根据PC中存放的指令地址，将指令从RAM读出写入指令寄 存器IR中，此过程称为“取指令”，与此同时，PC中的地址自动加1，指向下一 条指令在RAM中的存放地址。跳转指令如JMP、JZ、JC让程序跳转至指定地址去执 行，这时PC需要装载跳转地址。因此，指令计数器PC的接口及功能如下：</p>
<table>
<thead>
<tr>
<th>CLK</th>
<th>INPC</th>
<th>LDPC</th>
<th>功能</th>
</tr>
</thead>
<tbody><tr>
<td>下边沿</td>
<td>1</td>
<td>0</td>
<td>c[7..0]中数据自加1</td>
</tr>
<tr>
<td>下边沿</td>
<td>0</td>
<td>1</td>
<td>a[7..0]向入c[7..0]</td>
</tr>
</tbody></table>
<h5 id="仿真验证-7"><a href="#仿真验证-7" class="headerlink" title="仿真验证"></a>仿真验证</h5><p><img src="https://i.loli.net/2021/04/14/UuT9rDWgOhZnstw.png" alt="6"></p>
<p>PC指令计数器需要完成地址赋值与自加1的操作。</p>
<p>当t=250ns，时钟下边沿到来，IN_PC为1，输入为10100001，c中输出地址自加1，变成00000001.</p>
<p>当t=650ns，时钟下边沿到来，LDPC为1，输入为10100001，此时将输入端口a中数据发送到c，c输出10100001.</p>
<h4 id="9-RAM"><a href="#9-RAM" class="headerlink" title="9.RAM"></a>9.RAM</h4><h5 id="接口实现-8"><a href="#接口实现-8" class="headerlink" title="接口实现"></a>接口实现</h5><img src="https://i.loli.net/2021/04/14/qyrw4cd91NJUGbK.png" alt="RAM" style="zoom:80%;" />

<h5 id="功能实现-8"><a href="#功能实现-8" class="headerlink" title="功能实现"></a>功能实现</h5><p>随机存储器RAM是与CPU直接交换数据的内部存储器，也叫主存(内存）。它可以随时读写，而且速度很快，通常作为操作系统或其他正在运行中的程序的临时数据存储媒介。</p>
<table>
<thead>
<tr>
<th>CLK</th>
<th>WE(XL)</th>
<th>OUTENAB(DL)</th>
<th>FUNCTION</th>
</tr>
</thead>
<tbody><tr>
<td>上边沿</td>
<td>0</td>
<td>0</td>
<td>Dio&lt;=高阻态Z</td>
</tr>
<tr>
<td>上边沿</td>
<td>1</td>
<td>0</td>
<td>Dio的数据写入address所指定的存储单元</td>
</tr>
<tr>
<td>上边沿</td>
<td>0</td>
<td>1</td>
<td>address所指定的存储单元数据从dio输出</td>
</tr>
</tbody></table>
<p>其中端口outenab为输出使能端，XL为使能端（读入数据),ADDR[7..0]指定访问RAM的地址，加载时钟CLK，XL为1，将外部输入DATAIN[7..0] 写入RAM的对应存储单元。图中TRI为三态缓存元件，上部为使能端口。</p>
<p>定制ram时，有许多选项</p>
<table>
<thead>
<tr>
<th>LPM_ADDRESS_CONTROL</th>
<th>Should the address and control ports be registered?地址是否需要被控制端口寄存</th>
</tr>
</thead>
<tbody><tr>
<td>LPM_FILE</td>
<td>File containing initial contents of memory array.包含内存单元的初始文件</td>
</tr>
<tr>
<td>LPM_INDATA</td>
<td>Should the write data be registered?写入数据是否需要寄存？</td>
</tr>
<tr>
<td>LPM_NUMWORDS</td>
<td>Number of memory words, default is 2^LPM_WIDTHAD.内存字节，默认为2^LPM_WIDTHAD</td>
</tr>
<tr>
<td>LPM_OUTDATA</td>
<td>Should the output data be registered?输出数据是否需要寄存？</td>
</tr>
<tr>
<td>LPM_WIDTH</td>
<td>Data width in bits, any integer &gt; 0.数据位宽。</td>
</tr>
<tr>
<td>LPM_WIDTHAD</td>
<td>Number of address lines, any integer &gt; 0.地址行数</td>
</tr>
</tbody></table>
<h5 id="仿真验证-8"><a href="#仿真验证-8" class="headerlink" title="仿真验证"></a>仿真验证</h5><p><img src="https://i.loli.net/2021/04/14/KNAltsHXIi4gQBn.png" alt="14"></p>
<p>t=40ns，时钟上边沿到来，DATAIN=11110000，将数据从dio端口写入地址为00000000的单元中，当t=370ns时，DL=1，将地址为00000000的数据读取到dio，输出11110000。</p>
<h4 id="10-SM"><a href="#10-SM" class="headerlink" title="10.SM"></a>10.SM</h4><h5 id="接口实现-9"><a href="#接口实现-9" class="headerlink" title="接口实现"></a>接口实现</h5><p><img src="https://i.loli.net/2021/04/14/iZMlSxRorfWmDyV.png" alt="SM"></p>
<h5 id="功能实现-9"><a href="#功能实现-9" class="headerlink" title="功能实现"></a>功能实现</h5><p>模型机中所有指令的执行都是一个周期完成取指令，一个周期执行指令。如 何区分当前周期是取指令还是执行呢？这就需要SM。当SM=0时，该周期完成取指 令，当SM=1时，该周期执行指令。SM的功能及接口如下：</p>
<table>
<thead>
<tr>
<th>CLK</th>
<th>EN</th>
<th>功能</th>
</tr>
</thead>
<tbody><tr>
<td>下边沿</td>
<td>1</td>
<td>SM取反</td>
</tr>
<tr>
<td>下边沿</td>
<td>0</td>
<td>SM不变</td>
</tr>
</tbody></table>
<h5 id="仿真验证-9"><a href="#仿真验证-9" class="headerlink" title="仿真验证"></a>仿真验证</h5><p><img src="https://i.loli.net/2021/04/14/uX2SRT7Gw6KhHCy.png" alt="2"></p>
<p>CLK下边沿跳转时，EN=1</p>
<p>z从0到1进行跳转。EN=0，z保持不变。</p>
<h2 id="4-系统测试"><a href="#4-系统测试" class="headerlink" title="4.系统测试"></a>4.系统测试</h2><h3 id="4-1测试环境"><a href="#4-1测试环境" class="headerlink" title="4.1测试环境"></a>4.1测试环境</h3><p><strong>测试软件</strong>：Quartus II 9.0 </p>
<p><strong>测试系统环境</strong>：Windows10 专业版64bit </p>
<h3 id="4-2测试代码"><a href="#4-2测试代码" class="headerlink" title="4.2测试代码"></a>4.2测试代码</h3><p>第一段代码：</p>
<p><img src="https://i.loli.net/2021/04/14/lkDVXPG1TEo6xvN.png" alt="cod1"></p>
<table>
<thead>
<tr>
<th>代码</th>
<th>操作</th>
</tr>
</thead>
<tbody><tr>
<td>00100000</td>
<td>输入操作，将输入数据11000000存入寄存器A</td>
</tr>
<tr>
<td>01000000</td>
<td>输出操作，将输出数据输出到发光二极管，应为A寄存器中值11000000</td>
</tr>
<tr>
<td>11110100</td>
<td>MOVA操作,将A寄存器中数据存入寄存器B中，寄存B中的值应变为11000000</td>
</tr>
<tr>
<td>10110010</td>
<td>OR操作，将A，C寄存器中的数据11000000和00000000进行取或操作，并存入A寄存器</td>
</tr>
<tr>
<td>01010000</td>
<td>NOT操作，将A中的值取反后，存入寄存器A，应为00111111</td>
</tr>
<tr>
<td>01100100</td>
<td>SUB操作，将寄存器B数据减去A中数据，B应为 10000001</td>
</tr>
<tr>
<td>10010001</td>
<td>ADD操作，将寄存器A,B数相加后存入寄存器A中</td>
</tr>
<tr>
<td>00110000</td>
<td>JMP指令，跳转到内存下一位指示地址0001000处。</td>
</tr>
<tr>
<td>11110111</td>
<td>MOVC指令，从寄存器C中读出地址00000000，将RAM中该地址值存入B中</td>
</tr>
</tbody></table>
<table>
<thead>
<tr>
<th>代码</th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td>11000000</td>
<td>HALT指令，不再工作</td>
</tr>
</tbody></table>
<p>第二段代码</p>
<p><img src="https://i.loli.net/2021/04/14/HUJztPoBKqZbja1.png" alt="cod2"></p>
<p>先进行运算使得Zf，Cf为1得到JZ，JC指令得以运行，在进行验证操作,首先输入10100000，以得到进位Cf。JC跳转后，再执行输入10100011，得到Zf。</p>
<table>
<thead>
<tr>
<th>代码</th>
<th>指令</th>
</tr>
</thead>
<tbody><tr>
<td>00110010</td>
<td>JC指令，取内存下一位对应地址00001000处继续执行</td>
</tr>
<tr>
<td>00110001</td>
<td>JZ指令，取内存下一位对应地址00010000处继续执行</td>
</tr>
<tr>
<td>11111100</td>
<td>MOVB指令，读出寄存器A中的值和寄存器C中的值，将寄存器A的值写入RAM中地址为寄存器C中的值的单元</td>
</tr>
<tr>
<td>01110000</td>
<td>NOP指令，执行时PC+1</td>
</tr>
<tr>
<td>10100011</td>
<td>RSL指令，将A寄存器数据循环左移后存入A</td>
</tr>
<tr>
<td>10100000</td>
<td>RSR指令，将A寄存器数据循环右移后存入A</td>
</tr>
</tbody></table>
<h3 id="4-3测试结果"><a href="#4-3测试结果" class="headerlink" title="4.3测试结果"></a>4.3测试结果</h3><p>第一段代码</p>
<p><img src="https://i.loli.net/2021/04/14/XkTY6WISLyCOBJA.png" alt="11"></p>
<p><img src="https://i.loli.net/2021/04/14/dVqobG7IuFpaLm9.png" alt="12"></p>
<p><img src="https://i.loli.net/2021/04/14/2hHrzx1Gona85Iq.png" alt="13"></p>
<ol>
<li><p>0-20ns,执行IN指令，输入11000000。</p>
</li>
<li><p>30-40ns执行OUT指令，输出寄存器中值1100000.</p>
</li>
<li><p>50-60ns执行MOVA指令，将A将A寄存器中数据存入寄存器B中，寄存B中的值变为11000000</p>
</li>
<li><p>70-80ns执行OR指令，将A，C寄存器中的数据11000000和00000000进行取或操作，并存入A寄存器，数据不变。</p>
</li>
<li><p>90-100ns执行NOT指令，将A中的值取反后，存入寄存器A数据为00111111</p>
</li>
<li><p>110-120ns执行SUB操作，将寄存器B数据减去A中数据，B中数据为10000001</p>
</li>
<li><p>130-140ns执行ADD操作，将寄存器A,B数相加后存入寄存器A中，结果为1100000</p>
</li>
<li><p>150-160ns执行JMP操作，跳转到地址0001000</p>
</li>
<li><p>170-180ns执行MOVC指令，从寄存器C中读出地址00000000，将RAM中该地址值存入B中，B中数据为00100000</p>
</li>
<li><p>最后HALT指令进行停机</p>
<p>验证正确</p>
</li>
</ol>
<p>第二段代码</p>
<p><img src="https://i.loli.net/2021/04/14/vlVzqeBXtgE3WD8.png" alt="21"></p>
<p><img src="https://i.loli.net/2021/04/14/FBm7Gv1CV3o2cxJ.png" alt="24"></p>
<p><img src="https://i.loli.net/2021/04/14/Nrnc8i3KLl2ap7Z.png" alt="25"></p>
<ol>
<li><p>60ns时，Cf=1，执行JC指令，取内存下一位对应地址00001000处继续执行</p>
</li>
<li><p>140ns时，Zf=1，执行JZ指令，取内存下一位对应地址00010000处继续执行</p>
</li>
<li><p>170ns时，执行MOVB指令，读出寄存器A中的值和寄存器C中的值，将寄存器A的值写入RAM中地址为寄存器C中的值的单元</p>
</li>
<li><p>180ns时，执行NOP指令，执行时PC+1，执行下一个指令。</p>
</li>
<li><p>200ns时，执行RSL指令，将A寄存器数据循环左移后存入A，数据应为01000111</p>
</li>
<li><p>220ns时，执行RSR指令，将A寄存器数据循环右移后存入A，数据应为10100011</p>
<p>指令全部验证成功</p>
</li>
</ol>
<h3 id="4-4模型机性能分析"><a href="#4-4模型机性能分析" class="headerlink" title="4.4模型机性能分析"></a>4.4模型机性能分析</h3><p><img src="C:\Users\shentio\Desktop\LCDF_LAB\lab_end\rep\性能.png" alt="性能"></p>
<p>消耗204个逻辑门，占用7%</p>
<p><img src="https://i.loli.net/2021/04/14/MB7zyluJDaTqid9.png" alt="fmax"></p>
<h2 id="5-总结"><a href="#5-总结" class="headerlink" title="5.总结"></a>5.总结</h2><ol>
<li><p>减少开销可以：一定情况下在VHDL中将if语句改为when select，这样的单变量选择可以减少开销，但是串行会增加延时。优化逻辑结构，我们要合理的简化设计，精简逻辑，达到最优的效果。</p>
</li>
<li><p>避免触发器的不必要生成，尽量将每个模块进行逻辑划分，相互之间没有交集，避免多余的触发器生成。</p>
</li>
<li><p>中间变量的使用，用一个内部变量来临时存储一个值，当需要改变的时候就去改变它，这个功能类似于寄存器。</p>
</li>
<li><p>每个模块单独验证的必要性，如果直接将整合好的CPU进行验证，逻辑将十分复杂与困难。</p>
</li>
<li><p>沟通交流十分重要，如果没有讨论，一个人很难完成，但是讨论不意味着全套照搬，而是吸收思想，自己实现。</p>
</li>
</ol>

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class="nav-number">3.2.</span> <span class="nav-text">3.2各模块的具体实现</span></a><ol class="nav-child"><li class="nav-item nav-level-4"><a class="nav-link" href="#1-%E6%8C%87%E4%BB%A4%E8%AF%91%E7%A0%81%E5%99%A8%E4%B8%8E%E6%8E%A7%E5%88%B6%E4%BF%A1%E5%8F%B7%E4%BA%A7%E7%94%9F%E9%80%BB%E8%BE%91"><span class="nav-number">3.2.1.</span> <span class="nav-text">1.指令译码器与控制信号产生逻辑</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0"><span class="nav-number">3.2.1.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0"><span class="nav-number">3.2.1.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81"><span class="nav-number">3.2.1.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li><li class="nav-item nav-level-4"><a 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nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0-2"><span class="nav-number">3.2.3.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0-2"><span class="nav-number">3.2.3.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81-2"><span class="nav-number">3.2.3.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li><li class="nav-item nav-level-4"><a class="nav-link" href="#4-%E7%A7%BB%E4%BD%8D%E9%80%BB%E8%BE%91"><span class="nav-number">3.2.4.</span> <span class="nav-text">4.移位逻辑</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0-3"><span class="nav-number">3.2.4.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0-3"><span class="nav-number">3.2.4.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81-3"><span class="nav-number">3.2.4.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li><li class="nav-item nav-level-4"><a class="nav-link" href="#5-CF-ZF%E8%A7%A6%E5%8F%91%E5%99%A8"><span class="nav-number">3.2.5.</span> <span class="nav-text">5.CF,ZF触发器</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0-4"><span class="nav-number">3.2.5.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0-4"><span class="nav-number">3.2.5.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81-4"><span class="nav-number">3.2.5.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li><li class="nav-item nav-level-4"><a class="nav-link" href="#6-IR%E5%AF%84%E5%AD%98%E5%99%A8"><span class="nav-number">3.2.6.</span> <span class="nav-text">6.IR寄存器</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0-5"><span class="nav-number">3.2.6.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0-5"><span class="nav-number">3.2.6.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81-5"><span class="nav-number">3.2.6.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li><li class="nav-item nav-level-4"><a class="nav-link" href="#7-%E9%80%9A%E7%94%A8%E5%AF%84%E5%AD%98%E5%99%A8%E7%BB%84"><span class="nav-number">3.2.7.</span> <span class="nav-text">7.通用寄存器组</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0-6"><span class="nav-number">3.2.7.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0-6"><span class="nav-number">3.2.7.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81-6"><span class="nav-number">3.2.7.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li><li class="nav-item nav-level-4"><a class="nav-link" href="#8-%E6%8C%87%E4%BB%A4%E8%AE%A1%E6%95%B0%E5%99%A8PC"><span class="nav-number">3.2.8.</span> <span class="nav-text">8.指令计数器PC</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0-7"><span class="nav-number">3.2.8.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0-7"><span class="nav-number">3.2.8.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81-7"><span class="nav-number">3.2.8.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li><li class="nav-item nav-level-4"><a class="nav-link" href="#9-RAM"><span class="nav-number">3.2.9.</span> <span class="nav-text">9.RAM</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0-8"><span class="nav-number">3.2.9.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0-8"><span class="nav-number">3.2.9.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81-8"><span class="nav-number">3.2.9.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li><li class="nav-item nav-level-4"><a class="nav-link" href="#10-SM"><span class="nav-number">3.2.10.</span> <span class="nav-text">10.SM</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E6%8E%A5%E5%8F%A3%E5%AE%9E%E7%8E%B0-9"><span class="nav-number">3.2.10.1.</span> <span class="nav-text">接口实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%8A%9F%E8%83%BD%E5%AE%9E%E7%8E%B0-9"><span class="nav-number">3.2.10.2.</span> <span class="nav-text">功能实现</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E9%AA%8C%E8%AF%81-9"><span class="nav-number">3.2.10.3.</span> <span class="nav-text">仿真验证</span></a></li></ol></li></ol></li></ol></li><li class="nav-item nav-level-2"><a class="nav-link" href="#4-%E7%B3%BB%E7%BB%9F%E6%B5%8B%E8%AF%95"><span class="nav-number">4.</span> <span class="nav-text">4.系统测试</span></a><ol class="nav-child"><li class="nav-item nav-level-3"><a class="nav-link" href="#4-1%E6%B5%8B%E8%AF%95%E7%8E%AF%E5%A2%83"><span class="nav-number">4.1.</span> <span class="nav-text">4.1测试环境</span></a></li><li class="nav-item nav-level-3"><a class="nav-link" href="#4-2%E6%B5%8B%E8%AF%95%E4%BB%A3%E7%A0%81"><span class="nav-number">4.2.</span> <span class="nav-text">4.2测试代码</span></a></li><li class="nav-item nav-level-3"><a class="nav-link" href="#4-3%E6%B5%8B%E8%AF%95%E7%BB%93%E6%9E%9C"><span class="nav-number">4.3.</span> <span class="nav-text">4.3测试结果</span></a></li><li class="nav-item nav-level-3"><a class="nav-link" href="#4-4%E6%A8%A1%E5%9E%8B%E6%9C%BA%E6%80%A7%E8%83%BD%E5%88%86%E6%9E%90"><span class="nav-number">4.4.</span> <span class="nav-text">4.4模型机性能分析</span></a></li></ol></li><li class="nav-item nav-level-2"><a class="nav-link" href="#5-%E6%80%BB%E7%BB%93"><span class="nav-number">5.</span> <span class="nav-text">5.总结</span></a></li></ol></div>
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